1. Field of Invention
The present invention relates to a layout method of a semiconductor integrated circuit, performed on a computer, a layout structure of a semiconductor integrated circuit designed with the layout method, and a photomask used for manufacturing a semiconductor integrated circuit having the layout structure.
2. Description of Related Art
For designing layouts of semiconductor integrated circuits, standard cell methods have been widely used with the advance of CAD (Computer Aided Design) tools. According to a standard cell method, a plurality of standard cells having circuit patterns for realizing basic logical functions such as an NAND gate, a flip-flop, and the like, are designed, and operations of the standard cells are verified beforehand. Thus, designed and verified standard cells are registered in a library. The user selects specific standard cells for realizing desired logical functions from the library, and arranges these cells so as to be electrically interconnected to one another on a CAD tool, whereby a semiconductor integrated circuit having desired logical functions is thus designed.
With conventional techniques, in general, a plurality of standard cell rows, each of which is formed of a plurality of standard cells, are formed. Then, the plurality of standard cell rows is arranged with wiring channels between them, whereby a two-dimensional array of the standard cells (which will be referred to as “standard-cell array” hereafter) is thus formed. However, recently available multilevel interconnections of five layers or more, for example, allows the interconnection of the standard cells without forming the wiring channels. Thus, “channel-less” type standard cell arrays, in which the standard cells are two-dimensionally arranged in rows and columns without the wiring channels are becoming widespread. See Japanese Unexamined Patent Application Publication No. 2002-313937 (Patent Document 1), for example.
Hereafter, the direction wherein a plurality of standard cells is arranged so as to form a standard cell row will be referred to as the horizontal direction in this application. Moreover, the direction perpendicular to the horizontal direction in the same plane, i.e., the direction wherein the plurality of standard cell rows are arranged so as to form a standard cell array, will be referred to as “vertical direction”. Furthermore, the dimension of the standard cell in the horizontal direction will be referred to as a “width”, and the dimension in the vertical direction will be referred to as “height” hereafter.
The standard cells forming a channel-less type standard cell array disclosed in Patent Document 1 have the same common height, and different widths that correspond to their functions. According to Patent Document 1, the standard cells are arranged along a plurality of parallel lines, whereby a plurality of standard cell rows with the same “width H” (which corresponds to the “height” in this application) are formed. The spaces between the adjacent standard cell rows are removed by sharing the power supply wiring and the ground wiring with the adjacent standard cell rows. Thus, a channel-less type standard cell array is formed.
On the other hand, the process margin is constantly decreasing with the rapid advance of fine patterning used for manufacturing semiconductor integrated circuits. In particular, while processing in an area where the patterns having the same dimension are arranged with a uniform density can be made with relative ease, it is generally extremely difficult to make processing in an area with sufficient precision where the patterns have low uniformity.
For example, the portion within a standard cell array contains device patterns of the standard cells, e.g., gate layer patterns, with high density. Accordingly, the patterns are arranged with high uniformity in this area. However, the patterns are arranged in the area outside of the standard cell array at a very low density compared with the area within the standard cell array. Accordingly, it is difficult to achieve processing of device patterns with sufficient precision in the outer-most portions of the standard cell array.
In a case where exposing light irradiates a semiconductor substrate having a positive-type photo resist layer, through a mask having a mask pattern, ideally, the exposing light does not irradiate the area where the mask pattern is provided. Therefore, the resist layer on these areas is not exposed.
However, in reality, some of the exposing light reaches even the area on the semiconductor substrate where the mask pattern is provided, due to scattering of the exposing light passing through the space between the mask patterns. As a result, the resist in the area, which is not to be exposed, is partially exposed. With the decrease of the pattern dimension, such unintended exposure of the resist layer becomes a significant problem.
Even in such a situation, the region having high uniformity of pattern density, e.g., the region within the inner portion of the standard cell array, can be processed with sufficient precision. That is, correction of the mask pattern by giving consideration to the resist pattern deformations due to the scattered light, or an optical proximity correction (OPC), can be effectively performed to the region having high uniformity of pattern density. In addition, the optimization of exposure conditions may also be effective for the region having high uniformity of pattern density.
However, at the outermost portion of the standard cell array, a greater amount of the unintended exposure occurs because of the scattering of the exposing light that passes through the area outside of the standard cell array, which has a low pattern density. As a result, a greater deformation of the resist pattern occurs at the outermost portion of the standard cell array compared to the internal portion. Even in such a region, the mask pattern could be extensively corrected correspondingly to the large resist pattern deformation. However, such extensive correction generally leads to a reduction of process margin. That is, this leads to the problem of the resist pattern becoming susceptible to significant dimensional deviation due to deviation in the exposure light intensity, the deviation of the focus, and so on, over the exposed area. As a result, the resist pattern formed at the outermost portion of the standard cell array has in general a much poorer precision compared to the inner portion of the standard cell array.
A technique is known in which “dummy” patterns are arranged in regions having small pattern density, i.e., the regions having no device patterns, in order to improve the flatness of the surface of a semiconductor integrated circuit. See Japanese Unexamined Patent Application Publication No. 2002-9161 (Patent Document 2), for example. The dummy pattern provides no logical function for the semiconductor integrated circuit.
With the technique disclosed in Patent Document 2, two data are separately created on a CAD tool. The first one is a data in which the dummy pattern cells each having a dummy pattern are arranged over the entire chip area where the device structures of the semiconductor integrated circuit is to be formed. The second one is a data in which device patterns for realizing logical functions of the semiconductor integrated circuit, such as active region patterns, well patterns, gate electrode patterns, and so on, are arranged in the same chip area. Subsequently, these two data of the chip area are superimposed by logical synthesizing, whereby a data of the chip area, in which both of the device patterns and the dummy cells are arranged, is created. It should be noted that, in the logical synthesizing, the dummy cells that overlap the device patterns are deleted. In general, on the chip area thus designed, the dummy cells are arranged so as to surround the device patterns.
However, in the technique disclosed in Patent Document 2, there is a need to maintain a margin between the dummy pattern and the device pattern for ensuring an electrical isolation between the two patterns and for accounting for any error in the mask alignment. Accordingly, dummy cells are deleted over a region larger than the region where the device patterns are arranged by a certain margin. This procedure leads to the creation of a gap between the device pattern and the dummy cell.
Furthermore, there is no relationship between the layout of the dummy cells and the layout of the device pattern. That is, there is no relationship between the grids used in the CAD tool on which the dummy cells are placed and the grids on which the device patterns are placed. Accordingly, the size of the gap between the device pattern and the dummy cell remaining after they are superimposed on each other differs for each device pattern.
Accordingly, even if the dummy pattern arranging technique disclosed in Patent Document 2 is applied to a standard cell array disclosed in Patent Document 1, gaps with varying sizes will be formed between the standard cells arranged in the outermost portion of the standard cell array and the dummy cells.
In such a layout, while the uniformity of pattern density is improved as compared to a layout having no dummy pattern, the uniformity is not enough to be used in advanced fine patterning technology. Accordingly, the combination of these conventional technologies presents difficulties in achieving processing with the high precision required for further advanced fine-patterning technology.
Furthermore, a great amount of calculations are required for the logical synthesizing in the technique disclosed in Patent Document 2. Accordingly, an extremely long time is required for the layout design.